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| 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs March 1994 Revised March 2005 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs General Description The ABT240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. Features s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number 74ABT240CSC 74ABT240CSJ 74ABT240CMSA 74ABT240CMTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names OE1, OE2 Description 3-STATE Output Enable Inputs I0-I7 O0-O7 Inputs Outputs Truth Tables Inputs OE1 L L H Inputs OE2 L L H H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Outputs In L H X (Pins 12, 14, 16, 18) H L Z Outputs In L H X (Pins 3, 5, 7, 9) H L Z (c) 2005 Fairchild Semiconductor Corporation DS011664 www.fairchildsemi.com 74ABT240 Absolute Maximum Ratings(Note 1) Storage Temperature Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current (Across Comm Operating Range) Over Voltage Latchup (I/O) twice the rated IOL (mA) 65qC to 150qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Enable Input 50 mV/ns 20 mV/ns 40qC to 85qC 4.5V to 5.5V 0.5V to 5.5V 0.5V to VCC 150 mA 10V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 Min 2.0 0.8 Typ Max Units V V V V V V Min Min Min Min Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN IOH IOH IOL VIN VIN VIN VIN VIN IID 1.2 18 mA 3 mA 32 mA 64 mA 2.7V (Note 3) VCC 7.0V 0.5V (Note 3) 0.0V 1.9 PA PA PA PA V 1 1 All Other Pins Grounded IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 3) Note 3: Guaranteed, but not tested. Note 4: For 8 bits toggling, ICCD 0.8 mA/MHz. 10 PA PA mA 0 5.5V VOUT 0 5.5V VOUT Max Max 0.0 Max Max Max VOUT VOUT VOUT 2.7V; OEn 0.5V; OEn 0.0V VCC 2.0V 2.0V 10 100 275 50 100 50 30 50 1.5 1.5 50 PA PA PA mA 5.5V; All Others GND All Outputs HIGH All Outputs LOW OEn VI VCC; VCC 2.1V VCC 2.1V VCC 2.1V PA mA mA All Others at VCC or Ground Enable Input VI Data Input VI Outputs Open Max OEn GND, (Note 4) One Bit Toggling, 50% Duty Cycle PA mA/ Max All Others at VCC or Ground No Load 0.1 MHz www.fairchildsemi.com 2 74ABT240 AC Electrical Characteristics TA VCC Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.0 1.6 1.1 1.1 1.8 1.6 CL 25qC 5V 50 pF Typ Max 4.8 4.8 6.2 6.2 6.4 5.8 TA 55qC to 125qC 4.5V-5.5V 50 pF Max 5.5 5.5 7.5 7.7 7.5 7.2 CL Min 0.8 1.0 0.8 0.8 1.0 1.0 TA 40qC to 85qC 4.5V-5.5V 50 pF Max 4.8 4.8 6.2 6.2 6.4 5.8 ns ns ns Units CL VCC VCC Min 1.0 1.6 1.1 1.1 1.8 1.6 Capacitance Symbol CIN COUT (Note 5) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0 1 MHz, per MIL-STD-883, Method 3012. Units pF pF VCC VCC 0V 5.0V Conditions TA 25qC Note 5: COUT is measured at frequency f 3 www.fairchildsemi.com 74ABT240 AC Loading *Includes jig and probe capacitance Standard AC Test Load Amplitude 3.0V Test Input Signal Requirements Test Input Signal Levels Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns AC Waveforms Propagation Delay, Pulse Width Waveforms Propagation Delay Waveforms for Inverting and Non-Inverting Functions 3-STATE Output HIGH and LOW Enable and Disable Times Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 4 74ABT240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74ABT240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74ABT240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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